佟星元,位康康

• 1:西安邮电大学电子工程学院

摘要(Abstract)：

对基于逐次逼近(SAR)模/数转换的高速模/数转换器(ADC)结构设计进行讨论。针对SAR ADC转换速率慢的缺点,分别探讨结合两步式结构、每步多比特结构以及多通道时间交织结构的3种高速SAR ADC系统架构。3种ADC系统架构上的优化不仅将SAR ADC推向了高速片上系统应用,还保持了其原有的低功耗优点。通过对基于SAR ADC的3种主流高速ADC的结构及原理进行研究,总结比较各自的优缺点,并阐述其在高速低功耗方向的发展趋势。

关键词(KeyWords)： 模/数转换器;逐次逼近;高速;低功耗

Abstract:

Keywords:

基金项目(Foundation): 国家自然科学基金资助项目(61204029);; 国家重大科技专项(2016ZX03001003-006);; 陕西省自然科学基金资助项目(2014JQ8332)

作者(Author): 佟星元,位康康

DOI: 10.13682/j.issn.2095-6533.2016.02.014

参考文献(References)：

• [1]佟星元.模/数转换器结构设计综述[J/OL],西安邮电大学学报,2013,18(2):75-79[2015-11-06].http://www.cnki.com.cn/Article/CJFDTotalXAYD201302016.htm.DOI:10.3969/j.issn.1007-3264.2013.02.015.
• [2]TONG X Y,YANG Y T,ZHU Z M,et al.High speed,high resolution and low power approaches for SAR A/D converter[C]//2009 WiCOM,Beijing of China:IEEE,2009:1-5.DOI:10.1109/WICOM.2009.5300895.
• [3]LEE C C,FLYNNl M P.A SAR-assisted Two-stage pipeline ADC[J].IEEE Journal of Solid-State Circuits,2011,46(4):859-869.DOI:10.1109/JSSC.2011.2108133.
• [4]WU J F,CHANG S J,LIN S H,et al.Low power pipelined SAR ADC with loading-free architecture[C]//2014VLSI-DAT,Hsin-Chu:IEEE,2014:1-4.DOI:10.1109/VLSI-DAT.2014.6834906.
• [5]CHIO U F,WEI H G,ZHU Y,et al.Design and experimental verification of a power effective flash-SAR subranging ADC[J].IEEE Trans.Cir.and Syst,II:Express Briefs,2010,57(8):607-611.DOI:10.1109/TCSII.2010.2050937.
• [6]LEE G Y,YOON K S.Design of a low power CMOS10bit flash-SAR ADC[C]//2014SOCC,Las Vegas of USA:IEEE,2014:88-91.DOI:10.1109/SOCC.2014.6948905.
• [7]TONG X Y,CHEN J M,ZHU Z M,et al.A high performance 90nm CMOS SAR ADC with hybrid architecture[J].Journal of Semiconductors,2010,31(1):1-7.DOI:10.1088/1674-4926/31/1/015002.
• [8]WEI H G,CHAN C H,CHIAO U,et al.An 8-b400-MS/s 2-b-per-cycle SAR ADC with resistive DAC[J].IEEE Journal of Solid-State Circuits,2012,47(11):2763-2772.DOI:10.1109/JSSC.2012.221418.
• [9]CAO Z H,YAN Y S.A 32mW 1.25GS/s 6b2b/Step SAR ADC in 0.13μm CMOS[J].IEEE Journal of Solid-State Circuits,2009,44(3):862-873.DOI:10.1109/JSSC.2008.2012329.
• [10]DAI G,CHEN C.A 400-MS/s 8-b 2-b/cycle SAR ADC with shared interpolator and alternative comparators[C]//2014 ISCAS,Melbourne of Australia:IEEE,2014:2365-2368.DOI:10.1109/ISCAS.2014.6865647.
• [11]HUANG H,GROZING M,JOHANNES D,et al.A6-GS/s 6-bit time interleaved SAR-ADC[C]//2013Microwave Integrated Circuits Conference,Nuremberg of Germany:IEEE,2013:37-40.
• [12]GRESHISHCHEV Y M,AGUIRRE J,BESSON M,et al.A 40GS/s 6b ADC in 65nm CMOS[C]//2010ISSCC,San Francisco of USA:IEEE,2010:390-391.DOI:10.1109/ISSCC.2010.5433972.
• [13]HARPE P,CANTATORE E,ROERMUND A V.A10b/12b40kS/s SAR ADC with Data-Driven Noise Reduction achieving up to 10.1bENOB at 2.2fJ/conversion-step,IEEE Journal of Solid-State Circuits,2013,48(12):3011-3018.DOI:10.1109/JSSC.2013.2278471.
• [14]Analog Devices.16-bit,1 MSPS SAR ADC[EB/OL].[2015-12-13].http://www.analog.com/cn/products/analog-to-digital-converters/ad-converters/ad7916.html.
• [15]HUANG G Y,CHANG S J,Lin Y Z,et al.A 10b200 MS/s 0.82mW SAR ADC in 40nm CMOS[C]//2013ASSCC,Singapore:IEEE,2013:289-292.DOI:10.1109/ASSCC.2013.6691039.
• [16]VARZAGHANI A,KASAPI A,LOIZOS D N,et al.A 10.3-GS/s,6-Bit Flash ADC for 10GEthernet Applications[J].IEEE Journal of Solid-State Circuits,2013,48(12):3038-3048.DOI:10.1109/JSSC.2013.2279419.
• [17]CAO Z H,YAN S L.A 52mW 10b210 MS/s twostep ADC for digital-IF receivers in 0.13μm CMOS[C]//2008 CICC,California of USA:IEEE,2008:309-312.DOI:10.1109/CICC.2008.4672083.