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为了改善在基于路径的忆阻逻辑计算框架中，将二元决策图（Binary Decision Diagrams,BDD）映射至忆阻交叉阵列时硬件开销过大的问题，提出一种基于BDD重排序优化的忆阻逻辑综合框架。该框架首创性地将自适应重启遗传算法（Adaptive Restart Genetic Algorithm,ARGA）用于BDD变量顺序优化，通过ARGA生成更适配忆阻交叉阵列的BDD结构，而ARGA中内置的自适应重启机制可保障BDD变量顺序优化的高效性，进而优化映射后阵列的行列数，有效减少硬件面积。对17个基准电路进行评估，实验结果表明，与改进前的忆阻逻辑框架相比，所提方法实现15%的阵列面积减少，并降低26%的运行能耗和12%的时延。且与COMPACT、CONTRA类型忆阻逻辑框架相比，运行能耗降低3～4个数量级，时延分别降低80%和97%。通过BDD结构与忆阻阵列映射约束的协同优化，为提升忆阻逻辑电路的综合效率提供了有效途径。
Abstract：To address the issue of excessive hardware overhead that arises when mapping binary decision diagrams(BDD)to memristor crossbar arrays within path-based memristive logic computing frameworks,a memristive logic synthesis framework based on BDD reordering optimization is proposed.The framework pioneers the application of the adaptive restart genetic algorithm(ARGA)to BDD variable order optimization,which generates BDD structures more suitable for mapping to memristor crossbar arrays,while its built-in adaptive restart mechanism ensures the efficiency of this optimization process which further optimizes the number of rows and columns in the mapped crossbar array,thereby effectively reducing hardware area.Evaluations were conducted on 17 benchmark circuits,and the experimental results show that compared with the original memristive logic framework,the proposed method reduces crossbar area by 15%,operation energy consumption by 26%,and latency by 12%.Moreover,in comparison with other memristive logic frameworks such as COMPACT and CONTRA,the proposed method reduces operation energy consumption by 3 and 4 orders of magnitude respectively,and decreases latency by 80% and 97%,respectively.Through the collaborative optimization of BDD structures and memristor array mapping constraints,this research provides an effective approach to enhance the synthesis efficiency of memristive logic circuits.
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基本信息:
DOI：10.13682/j.issn.2095-6533.2025.06.008
中图分类号:TP18;TN60
引用信息:
[1]刘鹏,朱亚军,姚廉,等.基于二元决策图重排序优化的忆阻逻辑综合框架[J].西安邮电大学学报,2025,30(06):68-76.DOI:10.13682/j.issn.2095-6533.2025.06.008.
基金信息:
国家自然科学基金项目(62374047,62174038); 计算机体系结构国家重点实验室开放课题(CLQ 202407)
2025-11-10
2025-11-10