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数字低压差稳压器(Digital Low Dropout Regulators, DLDO)由于数字兼容性高、可综合性强、工艺拓展及稳定性好的特点，在高效细粒度电源管理方面具有广泛应用。对传统DLDO工作原理进行了阐述，指出传统DLDO的瞬态响应被时钟频率所限制、能效偏低。针对同步、异步和比例-积分-微分(Proportional-Integral-Differential, PID)DLDO 3种主要的系统级架构进行稳定性分析，对比总结了自适应时钟、自偏置比较器、瞬态增强等能效提升技术。最后，汇总了现有代表性DLDO的性能指标和品质因数(Figure of Merit, FoM),并指明了DLDO的设计趋势和未来发展方向。
Abstract：Digital low dropout regulators(DLDO) has a wide range of applications in efficient fine-grained power management due to its high digital compatibility, comprehensibility, process expansion and stability.The working principle of conventional DLDOs is illustrated.The limitation of low energy efficiency of their transient response imposed by the clock frequency is pointed out.Stability analyses are conducted for three major system-level architectures, namely, synchronous, asynchronous, and proportional-integral-differential(PID) DLDOs, and comparisons are summarized for energy-efficiency enhancement techniques such as adaptive clocking, self-biased comparators, and transient enhancement.Finally, the performance indicators and figure of merit(FoM) of the existing representative DLDOs are summarized, and the design trends and the future development directions of DLDOs are indicated.
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基本信息:
DOI：10.13682/j.issn.2095-6533.2025.01.007
中图分类号:TM44;TN47
引用信息:
[1]沈祥,魏东东,辛昕,等.数字低压差稳压器综述[J].西安邮电大学学报,2025,30(01):58-65.DOI:10.13682/j.issn.2095-6533.2025.01.007.
基金信息:
中央高校基本科研业务费专项资金项目(ZYTS24025)
2025-01-10
2025-01-10